Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development

Katevenis, M.; Ammendola, R.; Biagioni, A.; Cretaro, P.; Frezza, O.; Cicero, F. Lo; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Simula, F.; Vicini, P.; Taffoni, G.; Pascual, J. A.; Navaridas, J.; Lujan, M.; Goodacre, J.; Lietzow, B.; Kersten, M. L.

Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development
M. Katevenis, R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero, A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Simula, P. Vicini, G. Taffoni, J. A. Pascual, J. Navaridas, M. Lujan, J. Goodacre, B. Lietzow, M. L. Kersten
In Microprocessors and Microsystems - Embedded Hardware Design 2018.
[bibtex] [url]

Bibtex Entry

@Article{KatevenisMMEHD2018,
  author       = "M. Katevenis and
                  R. Ammendola and
                  A. Biagioni and
                  P. Cretaro and
                  O. Frezza and
                  F. Lo Cicero and
                  A. Lonardo and
                  M. Martinelli and
                  P. S. Paolucci and
                  E. Pastorelli and
                  F. Simula and
                  P. Vicini and
                  G. Taffoni and
                  J. A. Pascual and
                  J. Navaridas and
                  M. Lujan and
                  J. Goodacre and
                  B. Lietzow and
                  M. L. Kersten",
  title        = "Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development",
  journal      = "Microprocessors and Microsystems - Embedded Hardware Design",
  year         = "2018",
  url          = "https://ivi.fnwi.uva.nl/isis/publications/2018/KatevenisMMEHD2018"
}