| Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development
M. Katevenis, R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero, A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Simula, P. Vicini, G. Taffoni, J. A. Pascual, J. Navaridas, M. Lujan, J. Goodacre, B. Lietzow, M. L. Kersten
In Microprocessors and Microsystems - Embedded Hardware Design 2018.
[bibtex] [url] |